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4 THE MICROARCHITECTURE LEVEL 1 MAR To and from main memory Memory control registers MDR PC MBR SP LV Control signals Enable onto B bus CPP Write C bus to register TOS OPC C bus B bus H A ALU control B 6 N Z ALU Shifter Shifter control 2 Figure 4-1. The data path of the example microarchitecture used in this chapter. 2222222222222222222222222222222222222222222222222 12222222222222222222222222222222222222222222222222 F 1 F 1 ENA 1 ENB 1 INVA 1 INC 1 Function 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 0 0 A 2222222222222222222222222222222222222222222222222 1 1 1 1 1 1 1 1 1 1 1 1 1 12222222222222222222222222222222222222222222222222 1 1 0 1 0 1 0 0 B 3 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 A 1 0 1 12222222222222222222222222222222222222222222222222 3 1 1 0 1 B 1 1 1 12222222222222222222222222222222222222222222222222 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 A+B 2222222222222222222222222222222222222222222222222 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 A+B+1 1 1 1 1 12222222222222222222222222222222222222222222222222 1 1 1 1 A+1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 12222222222222222222222222222222222222222222222222 1 1 0 1 0 1 B + 1 1 1 1 1 1 1 1 12222222222222222222222222222222222222222222222222 1 1 1 1 1 1 1 12222222222222222222222222222222222222222222222222 1 1 1 1 1 1 B−A 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 B−1 1 1 1 12222222222222222222222222222222222222222222222222 1 1 1 1 −A 1 0 1 12222222222222222222222222222222222222222222222222 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 A AND B 1 2222222222222222222222222222222222222222222222222 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 0 1 A OR B 1 1 1 1 12222222222222222222222222222222222222222222222222 1 1 0 1 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 12222222222222222222222222222222222222222222222222 0 1 0 0 0 1 1 1 1 1 1 1 1 1 12222222222222222222222222222222222222222222222222 11 1 1 1 1 1 1 12222222222222222222222222222222222222222222222222 1 1 0 1 −1 1 1 0 1 0 1 1 1 0 Figure 4-2. Useful combinations of ALU signals and the function performed. Registers loaded instantaneously from C bus and memory on rising edge of clock Shifter output stable Cycle 1 starts here Clock cycle 1 ∆w ∆x Set up signals to drive data path Drive H and B bus ∆y Clock cycle 2 New MPC used to load MIR with next microinstruction here ∆z ALU and shifter MPC available here Propagation from shifter to registers Figure 4-3. Timing diagram of one data path cycle. 32-Bit MAR (counts in words) Discarded 0 0 32-Bit address bus (counts in bytes) Figure 4-4. Mapping of the bits in MAR to the address bus. Bits 9 3 NEXT_ADDRESS Addr J M P C J A M N 8 J A M Z JAM S L L 8 9 3 4 S F0 F1 E E I I H O T C L S P M M W R F R P O P V P C D A R E E N N N N I T R R T A C A C S P A B V C 1 A E D H ALU C Mem B bus B B bus registers 0 = MDR 1 = PC 2 = MBR 3 = MBRU 4 = SP Figure 4-5. The microinstruction format for the Mic-1. 5 = LV 6 = CPP 7 = TOS 8 = OPC 9 -15 none Memory control signals (rd, wr, fetch) 3 4 4-to-16 Decoder MAR MDR MPC 9 PC O 8 MBR SP 512 × 36-Bit control store for holding the microprogram 8 LV JMPC CPP Addr J ALU C MIR M B TOS JAMN/JAMZ OPC H B bus 2 1-bit flip–flop N 6 ALU control High bit ALU Control signals Enable onto B bus Z Shifter C bus 2 Write C bus to register Figure 4-6. The complete block diagram of our example microarchitecture, the Mic-1. Address Addr JAM 0x75 0x92 001 Data path control bits JAMZ bit set … 0x92 … 0x192 One of these will follow 0x75 depending on Z Figure 4-7. A microinstruction with JAMZ set to 1 has two potential successors. SP LV SP LV SP LV a3 a2 a1 (a) 108 104 100 b4 b3 b2 b1 a3 a2 a1 c2 c1 b4 b3 b2 b1 a3 a2 a1 (b) (c) SP LV d5 d4 d3 d2 d1 a3 a2 a1 (d) Figure 4-8. Use of a stack for storing local variables. (a) While A is active. (b) After A calls B. (c) After B calls C. (d) After C and B return and A calls D. 
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, SP SP LV a2 a3 a2 a1 (a) LV a3 a2 a3 a2 a1 (b) SP LV a2 + a3 a3 a2 a1 (c) SP LV a3 a2 a2 + a3 (d) Figure 4-9. Use of an operand stack for doing an arithmetic computation.