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Overview Historically, the limiting factor in a computer’s performance has been memory access time – Memory speed has been slow compared to the speed of the processor – A process could be bottlenecked by the memory system’s inability to “keep up” with the processor EE 4504 Computer Organization Our goal in this section is to study the development of an effective memory organization that supports the processing power of the CPU Section 3 Computer Memory – General memory organization and performance – “Internal” memory components and their use – “External” memory components and their use Reading: Text, chapters 4 and 5 EE 4504 Section 3 1 EE 4504 Section 3 2 1 Terminology Capacity: the amount of information that can be contained in a memory unit -usually in terms of words or bytes Word: the natural unit of organization in the memory, typically the number of bits used to represent a number Addressable unit: the fundamental data element size that can be addressed in the memory -- typically either the word size or individual bytes Unit of transfer: The number of data elements transferred at a time -- usually bits in main memory and blocks in secondary memory Transfer rate: Rate at which data is transferred to/from the memory device EE 4504 Section 3 Access time: – For RAM, the time to address the unit and perform the transfer – For non-random access memory, the time to position the R/W head over the desired location Memory cycle time: Access time plus any other time required before a second access can be started Access technique: how are memory contents accessed – Random access: » Each location has a unique physical address » Locations can be accessed in any order and all access times are the same » What we term “RAM” is more aptly called read/write memory since this access technique also applies to ROMs as well » Example: main memory 3 EE 4504 Section 3 4 2 – Sequential access: » Data does not have a unique address » Must read all data items in sequence until the desired item is found » Access times are highly variable » Example: tape drive units – Direct access: » Data items have unique addresses » Access is done using a combination of moving to a general memory “area” followed by a sequential access to reach the desired data item » Example: disk drives EE 4504 Section 3 – Associative access: » A variation of random access memory » Data items are accessed based on their contents rather than their actual location » Search all data items in parallel for a match to a given search pattern » All memory locations searched in parallel without regard to the size of the memory Extremely fast for large memory sizes » Cost per bit is 5-10 times that of a “normal” RAM cell » Example: some cache memory units 5 EE 4504 Section 3 6 3 Memory Hierarchy Major design objective of any memory system Basis of the memory hierarchy – Registers internal to the CPU for temporary data storage (small in number but very fast) – External storage for data and programs (relatively large and fast) – External permanent storage (much larger and much slower) – To provide adequate storage capacity at – An acceptable level of performance – At a reasonable cost Four interrelated ways to meet this goal – Use a hierarchy of storage devices – Develop automatic space allocation methods for efficient use of the memory – Through the use of virtual memory techniques, free the user from memory management tasks – Design the memory and its related interconnection structure so that the processor can operate at or near its maximum rate Characteristics of the memory hierarchy – Consists of distinct “levels” of memory components – Each level characterized by its size, access time, and cost per bit – Each increasing level in the hierarchy consists of modules of larger capacity, slower access time, and lower cost/bit Goal of the memory hierarchy – Try to match the processor speed with the rate of information transfer from the lowest element in the hierarchy EE 4504 Section 3 7 EE 4504 Section 3 8 4 Registers in the CPU Cache Main memory Memory Type Technology Size Access Time Cache Semiconductor RAM 128-512 KB 10 ns Main Memory Semiconductor RAM 4-128 MB 50 ns Magnetic Disk Hard Disk Gigabyte 10 ms, 10 MB/sec Optical Disk CD-ROM Gigabyte 300 ms, 600 KB/sec Magnetic Tape Tape 100s MB Sec-min., 10MB/min Disk cache Magnetic disk Optical disk Magnetic tape Typical memory Parameters The memory hierarchy EE 4504 Section 3 9 EE 4504 Section 3 10 5 The memory hierarchy works because of locality of reference Example: – – – – – Memory references made by the processor, for both instructions and data, tend to cluster together » Instruction loops, subroutines » Data arrays, tables – Keep these clusters in high speed memory to reduce the average delay in accessing data – Over time, the clusters being referenced will change -- memory management must deal with this Two-level memory system Level 1 access time of 1 us Level 2 access time of 10us Ave access time = H(1) + (1-H)(10) us Figure 4.2 2-level memory performance EE 4504 Section 3 11 EE 4504 Section 3 12 6 Main Memory Core memory Semiconductor memory – Used in generations 2 and 3 – Magnetic cores (toroids) used to store logical 0 or 1 state by inducing an E-field in them (hysteresis loop) » 1 core = 1 bit of storage – Required addressing and sensing wires ran through each core – Destructive readout – Obsolete » Replaced in the 1970s by semiconductor memory EE 4504 Section 3 – Typically random access – RAM: actually read-write memory » Dynamic RAM Storage cell is essentially a transistor acting as a capacitor Capacitor charge dissipates over time causing a 1 to flip to a zero Cells must be refreshed periodically to avoid this Very high packaging density » Static RAM: basically an array of flip-flop storage cells Uses 5-10x more transistors than similar dynamic cell so packaging density is 10x lower Faster than a dynamic cell 13 EE 4504 Section 3 14 7 – Read Only Memories (ROM) » “Permanent” data storage » ROMs Data is “wired in” during fabrication at a chip manufacturer’s plant Purchased in lots of 10k or more » PROMs Programmable ROM Data can be written once by the user employing a PROM programmer Useful for small production runs » EPROM Erasable PROM Programming is similar to a PROM Can be erased by exposing to UV light EE 4504 Section 3 » EEPROMS Electrically erasable PROMs Can be written to many times while remaining in a system Does not have to be erased first Program individual bytes Writes require several hundred usec per byte Used in systems for development, personalization, and other tasks requiring unique information to be stored » Flash Memory Similar to EEPROM in using electrical erase Fast erasures, block erasures Higher density than EEPROM 15 EE 4504 Section 3 16 8 – Organization » Each memory chip contains a number of 1bit cells 1, 4, and 16 million cell chips are common » Cells can be arranged as a single bit column (e.g., 4Mx1) or in multiple bits per address location (e.g., 1Mx4) » To reduce pin count, address lines can be multiplexed with data and/or as high and low halves Trade off is in slower operation » Typical control lines W* (write), OE* (output enable) for write and read operations CS* (chip select) derived from external address decoding logic RAS*, CAS* (row and column address selects) used when address is applied to the chip in 2 halves EE 4504 Section 3 Figure 4.8 256Kx8 memory from 256Kx1 chips 17 EE 4504 Section 3 18 9 Figure 4.9 1Mx8 memory from 256Kx1 chips EE 4504 Section 3 19 – Improvements to DRAM » Basic DRAM design has not changed much since its development in the 70s » Cache was introduced to improve performance Limited to no gain in performance after a certain amount of cache is implemented » Enhanced DRAM Add fast 1-line SRAM cache to DRAM chip Consecutive reads to the same line are from this cache and thus faster than the DRAM itself Tests indicate these chips can perform as well as tradition DRAM-cache combinations » Cache DRAM Use larger SRAM cache on the chip as a true multi-line cache Use it as a serial data stream buffer for EE 4504 Section 3 block data transfers 20 10