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Introduction to Computing Systems from bits & gates to C & beyond Chapter 8 Input/Output  Basic organization  Keyboard input  Monitor output  Interrupts  DMA Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside I/O Basics Definitions  Input  transfer data from the outside world to the computer: keyboard, mouse, scanner, bar-code reader, etc.  Output  transfer data from the computer to the outside: monitor, printer, LED display, etc.  Peripheral: any I/O device, including disks. LC-2 8-2 supports a keyboard and a monitor Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Device Registers  I/O Interface  Through a set of Device Registers:  Status register (device is busy/idle/error)  Data register (data to be moved to/from device)  The device registers can be read/written by the CPU  LC-2     KBDR: keyboard data register KBSR: keyboard status register CRTDR: monitor data register CRTST: monitor status register LC-2 8-3 KBSR CTRSR KBDR CTRDR •KBSR[15] - keyboard ready (new character available) •KBDR[7:0] - character typed (ASCII) •CTRSR[15] - CRT ready •CTRDR[7:0] - character to be displayed (ASCII) Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Addressing Device Registers Special I/O Instructions  Read or write a device register using specialized I/O instructions. Memory Mapped I/O  Use existing data movement instructions (Load & Store).  Map each device register to a memory address (fixed).  CPU communicates with the device registers as if they were memory locations. LC-2  Uses memory mapped I/O xF3FC xF3FF xF400 xF401 8-4 CRTSR CRTDR KBSR KBDR LC-2 memory map Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Synchronizing CPU and I/O Problem  Speed mismatch between CPU and I/O:  CPU runs at > 2 GHz, all I/O is much slower.  Example : Keyboard input is at irregular intervals.  Need a protocol to keep CPU & KBD synchronized Handshake synchronization  CPU checks the KBD Ready status bit.  If set, CPU reads the data register and resets the Ready bit.  Start over.  Make CPU-I/O interaction seem to be synchronous 8-5 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Polling v/s Interrupts (Who’s driving?)  Polling - CPU driving  CPU checks the ready bit of status register (as per program instructions).  If (KBSR[15] == 1) then load KBDR[7:0] to a register.  If the I/O device is very slow, CPU is busy waiting.  Interrupt - I/O driving  Event triggered - when the I/O device is ready, it sets a flag: the interrupt signal.  When interrupt is set, the CPU is forced to an interrupt service routine (ISR) which services the interrupting device.  There are different priority levels of interrupt.  Specialized instructions can mask an interrupt level. 8-6 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Polling Algorithm Algorithm  Input  The CPU loops checking the Ready bit  When bit is set, a character is available  CPU loads the character  Output  CPU loops checking the Ready bit  When bit is set, monitor is ready for next character  CPU stores a character in monitor data register 8-7 Details (Keyboard)  When key is struck  ASCII code of character goes into KBDR[7:0]  KBSR[15] (Ready Bit) is set to 1  Keyboard is locked until CPU reads KBDR  Then Ready Bit is cleared, keyboard is unlocked Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Polling Routines START LDI A B BRzp LDI BR .FILL .FILL R1, A START R0,B NEXT_TASK xF400 xF401 ;Loop if Ready not set ;If set, load char ;Address of KBSR ;Address of KBDR Input a character from keyboard START LDI A B 8-8 BRzp STI BR .FILL .FILL R1, A START R0,B NEXT_TASK xF3FC xF3FF Output a character to the monitor ;Loop if Ready not set ;If set, send char ;Address of CRTSR ;Address of CRTDR Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Keyboard Echo: combine the above START LDI BRzp LDI ECHO LDI BRzp STI BR KBSR .FILL KBDR .FILL CRTSR .FILL CRTDR .FILL 8-9 R1,KBSR START R0,KBDR R1,CRTSR ECHO R0,CRTDR NEXT_TASK xF3FC xF3FF xF400 xF401 ;Loop if KB not ready ;Get character ;Loop if MON not ready ;Send character ;Address of KBSR ;Address of KBDR ;Address of CRTSR ;Address of CRTDR Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Example: Print a string LEA R1,STR ;Load address of string LOOP LDR R0,R1,#0 ;get next char to R0 BRZ DONE ;string ends with 0 L2 LDI R3,CRTSR ;Loop until MON is ready BRzp L2 STI R0,CRTDR ;Write next character ADD R1,R1,#1 ; Set address to next char BR LOOP STR .STRINGZ "Char String" DONE HALT 8 - 10 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Interrupts - More  Interrupt mask register: each bit specifies whether the corresponding device is allowed to interrupt.  In the CPU, the control logic checks the INT bit before each instruction fetch stage. Interrupt mask register Interrupt lines  If INT is set:  (PC) is saved  PC  address of corresponding ISR  Change mask settings (allow nested interrupts)  ISR is executed  Reset mask settings  Saved PC is restored  How can CPU tell who interrupted? 8 - 11 CPU INT Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside Interrupt – Who called? How can CPU tell who interrupted?  Polling  Vectored Interrupts  Multiple CPU INT lines, each dedicated to a device or group of devices (Intel: INT0, INT1 …)  Each INT line sends the CPU to a specific ISR (Interrupt Service Routine).  The ISR must figure out who called if more than one device is associated with that INT line.  Daisy Chain     CPU sends an interrupt acknowledge (IACK) that is passed from one device to another. Interrupting device puts the address of its ISR on the Data Bus. Order of devices in the chain is the priority. Example: SCSII IACK 8 - 12 Data bus Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside DMA – Direct Memory Access DMA  A device specialized in transferring data between memory and an I/O device (disk).  CPU writes the starting address and size of the region of memory to be copied, both source and destination addresses. CPU memory DMA  DMA does the transfer in the background.  It accesses the memory only when the CPU is not accessing it (cycle stealing). 8 - 13 I/O Dev