Handbook of algorithms for physical design automation part 79.pdf (Sổ tay thuật toán)

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 762 Finals Page 762 10-10-2008 #27 Handbook of Algorithms for Physical Design Automation As mentioned in Section 36.2, CMP-induced metal dishing increases the line resistance. In addition, metal height can vary as a function of line width, local and global densities. It is critical to ensure the basic computational accuracy of RC extraction tools before including process variation effects. Silicon validation of parasitics helps in closing the loop between process realities and interconnect extraction [44]. 36.6.2 IMPACT OF SPATIAL VARIATION As device and interconnect dimensions continue to shrink, maintaining process uniformity is increasing in importance and difficulty [61]. The 2004 edition of the International Technology Roadmap for Semiconductors (ITRS) [25] lists the control of printed transistor gate length in the lithography process as falling short of expectations for the coming technology generations. Variability is happening at multiple scales in semiconductor manufacturing processes, but only the largest of these scales has been studied. Statistical metrology methods are now used to model the variation of different parameters not only across the wafer but also within the die itself. The modeling of both waferlevel and die-level spatial dependencies will become increasingly important for effective process control. The quality of planarization with CMP depends on the layout feature density uniformity. In addition, the features on each die follow a systematic within-die variation. Therefore, different devices within the wafer will exhibit similar characteristics even though they have different characteristics within the die [3]. This interaction between wafer and die variation, if not considered, leads to erroneous modeling as shown in Figure 36.23. Figure 36.23a displays a one-dimensional cross section through the wafer displaying the ILD thickness over a particular device. Although the die mean (or wafer-level trend) across the wafer shows a small curvature, the enclosing curvature of wafer and die variation is larger. A sampling of only one device on each die may erroneously assign both die and wafer variation to the wafer scale uniformity, as illustrated in Figure 36.23a. A control technique that tries to make these sampled values more uniform will be ineffective as shown in Figure 36.23b. A method to solve this sampling problem is to intensively sample the devices within the measured die in addition to sampling them across the wafer. However, this method comes with extra cost of gathering the measurements. An alternative approach, for example, in CMP, is to measure both a sparse and a dense region of the measured die to obtain a simple estimate for die variance [3]. Wafer/die samples Die size (a) Wafer-level trend Die size Wafer-level trend (b) FIGURE 36.23 (a) Wafer-level trend generated by single-point sampling within each die can be very different than the mean surface. (b) Control based on sampled surface may achieve erroneous uniformity. (From Boning, D., Chung, J., Ouma, D., and Divecha, R., Proceedings in Process Control, Diagnostics and Modeling in Semiconductor Manufacturing II, 1997.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 763 10-10-2008 #28 763 CMP Fill Synthesis: A Survey of Recent Studies 36.6.3 TOPOGRAPHY-AWARE OPTICAL PROXIMITY CORRECTION Depth of focus is the major contributor to lithographic process margin. One of the major causes of focus variation is imperfect planarization of fabrication layers. Presently, OPC (optical proximity correction) methods are oblivious to the predictable nature of focus variation arising from wafer topography. As a result, designers suffer from manufacturing yield loss, as well as loss of design quality through unnecessary guardbanding. Figure 36.24 shows how post-CMP thickness variation results in loss of CD (critical dimension) control. Figure 36.24a shows how post-CMP thickness in copper-oxide polishing will predictably change with the region pattern density. The depth-offocus (DOF) variation corresponding to the thickness variation severely affects metal patterning of the subsequent upper layer, as shown in Figure 36.24b. In this figure, t1 and t2 are post-CMP thickness variations over dense and sparse regions, respectively. Hence, to minimize the impact of pattern-dependent effects of the CMP process, the OPC methods should be aware of the post-CMP topography to assign appropriate defocus value for all the features with the same topography. A recent work by Gupta et al. [21] proposes a flow and methodology to drive OPC with a topography map of the layout that is generated by CMP simulation. The experimental results showed that the proposed topography-aware OPC can yield up to 67 percent reduction in edge placement errors at the cost of little increase in mask cost. 36.6.4 INTELLIGENT CMP FILL SYNTHESIS Current commercial CMP fill insertion tools such as Encounter from Cadence perform fill insertion after routing and before RC extraction. Upon analyzing the density and calculating the required amount of fill to be inserted, there are designated commands that set the metal fill parameters for a given metal layer, including minimum and maximum length and width of fill metal, keep-off distance, spacing between fill metal geometries, preferred and maximum metal density, and window size. In particular, to insert fill features, Encounter starts with bigger fills and makes them smaller as it goes along. It uses the maximum metal fill size specified until it is impossible to fit a piece of metal fill of that size into a particular area, then it uses successively smaller pieces of metal fill until reaching the t2 t1 Post-CMP (a) Metal layer (b) FIGURE 36.24 (a) Side view showing thickness variation over regions with dense and sparse layout. (b) Top view showing CD variation when a line is patterned over a region with uneven wafer topography, that is, under conditions of varying defocus. (From Gupta, P., Kahng, A. B., Park, C. -H., Samadi, K., and Xu, X., Proceedings of the SPIE, 2005.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 764 Finals Page 764 10-10-2008 #29 Handbook of Algorithms for Physical Design Automation minimum length [32]. CMP fill insertion tools, however, do not have much flexibility in controlling the impact of the added fill features on interconnect performance (i.e., they only have a set of rules to abide). Therefore, a more sophisticated fill insertion methodology is required. As the industry moves toward the 65 nm node and beyond, traditional fill synthesis methods reach their limits of usefulness. One indication of this is the emergence of the so-called recommended rules, for example, “it is better to have a small difference between the density values of adjacent windows,” or “it is better to maximize the overlap of fill shapes on adjacent layers to enable dummy via insertion.” Of course, the impact of fill synthesis on timing continues to be a key concern for the designer. It is increasingly difficult for a DRC platform to obtain an optimal, design-driven fill synthesis solution that meets all basic CMP design rules and as many recommended rules as possible, while minimizing the impact on timing. In this subsection, we sketch the anticipated features of a more sophisticated, dedicated CMP fill synthesis tool—intelligent fill synthesis—that can potentially reduce engineering effort while enhancing manufacturability (by increasing process and design latitudes). Hence, an intelligent fill synthesis must embody such features as the following [20]. • Multilayer density control. Post-CMP deposition of oxide in the back end is conformal; therefore, the topography variation in one layer is almost directly transferred to the upper layer, and the topography variation of the upper layer is added to that from the previous layer. Even when the density variation of one layer is small, it is possible to have large enough variation for the entire back-end stack to cause yield loss or to exceed DOF limits of lithography. Intelligent fill synthesis should perform concurrent minimization of the density variation of multiple layers, as well as that of each individual layer. • Model-based fill synthesis. Rule-based fill synthesis is based on concepts such as density or keep-off distance rules, which are applied to wiring segments that have less than certain threshold amounts of timing slack. Model-based fill synthesis, on the other hand, would use CMP models to identify regions where planarity is important (next to heavily loaded critical segments and below critical segments). The model-based approach has implicit tight coupling to a timer, and models the impact of fill on coupling capacitance. • Timing-driven fill synthesis. One of the largest concerns in fill synthesis, apart from meeting the CMP design rules, is the impact of fill insertion to the capacitances of the existing nets. An excessive increase in wire capacitance can cause a net to violate its setup timing constraint. A large value for keep-off distance reduces this danger but it erodes into available areas to insert fills and sometimes makes it impossible to meet the minimum density constraint. With timing-driven intelligent fill, the impact of inserting fills on timing is continually assessed, and the minimum keep-off distance for each net to meet the setup time constraint can be computed to avoid a wastefully large one-size-fits-all keep-off distance. In a more advanced, intelligent timing-driven fill flow, the impact of fill insertion on both wafer topography and timing would be analyzed and optimized concurrently. One additional advantage of timingdriven fill is that it can improve the hold-time slack of a net by deliberately and selectively introducing capacitance to that net. • Wire sizing. Changing the width of a wire has certain impact on the parasitics of the wire such as resistance and capacitance. For example, in an organic low-k/Cu system, widening a wire may result in reduced resistance not only because the wire gains width but also because wider wire suppresses metal thickness loss. To complement the execution of timing-driven fill, it is possible to bias the wires by some small amount (<10 percent) and gain small timing slack. This will increase the operating latitude of the circuit. Alternatively, the impact of the height variation of wires can be compensated by width sizing to tighten the distribution of wire parasitics for any given drawn width. Figure 36.25 shows a practical approach to intelligent timing-driven fill. In the following approach, after all the required fill has been inserted, the windows that are still violating the minimum density Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 CMP Fill Synthesis: A Survey of Recent Studies Finals Page 765 10-10-2008 #30 765 Timing-Driven Fill Loop: 0. Set an initial conservatism factor 1. Do (initial) RCX and STA 2. Identify timing-violating nets (TVNs) – i.e., timing-critical nets 3. Apply conservative net-protection (+keep-off distance and blocking M + 1/M − 1 layers) per TVN segment 4. Run (incremental) MC-Fill? target fill amount 5. PIL-FILL Synthesis: 5.1 Greedy insert fill in fill slack columns, targeting most-needy tiles and largest-slack nets first 5.2 After K fill shapes have been inserted, re-run (incremental) STA based on C’s 5.3 Iterate until all required fill has been inserted (or, until no timing constraint looks safe) – return to step 5 6. Update Conservatism 6.1 Analyze windows that violate min density constraints 6.2 Identify nets that belong to the windows that violate the constraints 6.3 Do (incremental) RCX and STA to change the conservatism factor of TVNs – return to Step 2 FIGURE 36.25 Timing-driven fill synthesis approach. (From Gupta, P., Kahng, A.B., Nakagawa, O.S., and Samadi, K., Proceedings of the International VLSI/ULSI Multilevel Interconnection Conference, 2005.) criteria are identified. Then all the nets belonging to these windows will be selected. To meet the density criteria the conservatism factor of TVNs must be updated by allowing the fill to be inserted. This is done in accordance with the results of an incremental RCX and STA (i.e., basically to update the timing slacks of TVNs). 36.7 CONCLUSION In this survey, an overview of CMP processes was presented. Different characterization and modeling approaches were investigated. Even though CMP is the planarizing technique of choice in silicon manufacturing processes, its effectiveness is dominated by the layout pattern density. One technique that designers and manufacturers use to uniform the layout pattern density is CMP fill insertion. CMP fill features are nonfunctional metal features that are added to the layout to make the layout pattern density uniform while not contributing to the logic of the circuits. However, before addressing the problem of filling the layout with fill features, the density of the layout must to be analyzed. Different density calculation approaches such as fixed dissection regime and multilevel density analyses have been presented. Next, different fill synthesis methods including density-driven, model-based, and auxiliary objective-driven have been introduced. Even though CMP fill features help in making the layout pattern density more uniform, they impact total and coupling interconnect capacitances. In this survey, several different fill patterning and modeling techniques that aim at accurately assessing the impact on interconnect capacitance have also been presented. Finally, the concept of intelligent fill (IF) has been introduced. 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Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 770 10-10-2008 #35 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C037 Finals Page 771 19-9-2008 #2 Analysis 37 Yield and Optimization Puneet Gupta and Evanthia Papadopoulou CONTENTS 37.1 Introduction.. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.2 Sources of Yield Loss . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.3 Yield Analysis .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.3.1 Parametric Yield Analysis .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.3.2 Random Defect Yield Modeling and Critical Area Computation . . .. . . . . . . . . . . . . . 37.3.2.1 Defect Models .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.4 Methods for Yield Optimization .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.4.1 Critical Area and Catastrophic Yield Optimization Methods . . . . . . . .. . . . . . . . . . . . . . 37.4.2 Design Rules . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.4.3 Corner-Based Design Analysis .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.4.4 Future of Parametric Yield Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.4.4.1 Methods for Systematic Variability . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.4.4.2 Statistical Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 37.5 Conclusion .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 771 774 775 775 776 778 783 783 785 786 786 787 787 787 787 In this chapter, we discuss yield loss mechanisms, yield analysis and common physical design methods to improve yield. Yield is defined as the ratio of the number of products that can be sold to the number of products that can be manufactured. To motivate the importance of yield, it is instructive to look at the economics of chip manufacturing. The estimated typical cost of a modern 300 mm or 12 in. wafer 0.13 µm process fabrication plant is $ 2–4 billion, a typical number of processing steps for a modern integrated circuit is more than 150, a typical production cycle-time is over six weeks, and individual wafers cost multiple thousands of dollars. Given the huge investments that this entails, consistent high yield is necessary for faster time to profit. 37.1 INTRODUCTION The total yield for an integrated circuit Ytotal can be expressed a follows: Ytotal = Yline × Ybatch (37.1) Here Yline denotes line yield or wafer yield that is the fraction of wafers which survive through the manufacturing line, and Ybatch is the fraction of integrated circuits which, on each wafer, are fully functional at the end of the line. A steep yield ramp implies a quicker path to high batch yield, and hence, volume production, which in turn, means higher profitability for the semiconductor manufacturer who operates under time-to-market pressures. 771

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