Handbook of algorithms for physical design automation part 77.pdf (Sổ tay thuật toán)

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 742 Finals Page 742 10-10-2008 #7 Handbook of Algorithms for Physical Design Automation this model takes the topography of the wafer into account and adjusts the polishing rate accordingly, it does not consider the bending of the polishing pad. Neither does it consider the fluid mechanics. The model is purely empirical and does not depend on the pressure. Because of these shortcomings, it has limited use in modeling the entire CMP process. Warnock et al. [71] propose another model that quantitatively analyzes the absolute and the relative polish rate for different sizes and pattern factors. This model defines the dependence of the polish rate on the wafer shape. In particular, it takes into account all possible geometrical cases, which makes it applicable to modeling of the entire CMP process. Finally, a model proposed by Yu et al. [74] considers the dependence of the RR on the asperity of the polishing pad. The surface height variation for a 200 µm × 200 µm pad is reported to be 100 µm. In addition, the model divides the Preston’s constant K into three different parts: (1) a constant only dependent on the pad roughness and its elasticity, (2) a factor determined by the surface chemistry, and (3) a constant that is related to the contact area. However, it is not clear how these asperities affect the global quality of planarization. A global planarization quantity of 200 Å over a distance of 0.5 cm is reported in Ref. [64]. This variation is much less than the reported polishing pad height variation (100 µm), making it unclear how the approach fits into a general CMP simulation. 36.3.2 OXIDE CMP MODELING Pattern density is a significant contributor to oxide CMP process quality. The Preston equation shows that the material RR is a linear function of the pressure, which is affected by the pattern density at the interface between polishing pad and wafer. However, pattern density calculation is not trivial. In fact, the effective density at a particular point on the die depends on the size of the neighboring area over which density is averaged. The weighting function is also a major factor because it captures the influence of the surrounding area on the local pressure. Modeling of CMP for oxide planarization is reduced to accurately calculating the local pressure, and hence the pattern density distribution across every die [47]. As described in the previous subsection, there are several models that have been proposed to account for pattern effects in CMP, but their applicability has been limited. The basic model in Ref. [47] is based on the work by Stine et al. [63]. In this model, the interlayer dielectric thickness z at location (x, y) is calculated as z= z0 − ( ρ Kt(x,y) ) 0 z0 − z1 − Kt + ρ0 (x, y)z1 t < (ρ0 z1 )/K t > (ρ0 z1 )/K (36.2) The constant K is the blanket wafer RR (i.e., where the density is 100 percent). The important element of this model is the determination of the effective initial pattern density ρ0 (x, y). Figure 36.5 defines the terms used in Equation 36.2. In Equation 36.2 when t < (ρ0 z1 )/K, the local step height has not been completely removed. However, when features are planarized for a long enough time (t > (ρ0 z1 )/K), local step height is completely removed and a linear relationship between pattern density and ILD thickness exists [63]. The planarization length, which captures pad deformation during the CMP process, determines the amount in which neighboring features affect pattern density at a spatial location on the die. Thickness profile of any arbitrary mask pattern, under same process conditions, can be determined using the effective local density and an analytic thickness model. This reduces the characterization step into a single phase where only the planarization length of the process is determined. Planarization length is also a useful metric in oxide CMP process optimization because it reduces the investigation of the entire die to smaller regimes according to the planarization length [47]. Ouma [47] proposes a characterization methodology for oxide CMP processes that includes (1) the use of an elliptic pattern density weighting function that which has better correspondence to the polish pad deformation, (2) a three-step effective pattern calculation scheme that uses fast Fourier Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 743 10-10-2008 #8 743 CMP Fill Synthesis: A Survey of Recent Studies Down areas Up areas Z1 Bias, B Z > Z0 − Z1 Z=0 Z0 Oxide Z < Z0 − Z1 Metal FIGURE 36.5 Dishing and erosion in copper CMP process. (From Ouma, D., Modeling of chemical– mechanical polishing for dielectric planarization, Ph.D. Dissertation, Department of Electric Engineering and Computer Science, MIT, Cambridge, 1998.) transforms (FFTs) for computational efficiency, and (3) the use of layout masks with step densities that facilitate the determination of the characteristic length (defined as the planarization length) of the elliptic function by introducing large abrupt post-CMP thickness variations. 36.3.3 COPPER CMP MODELING Unlike oxide CMP, which involves the removal of only oxide material, the copper CMP involves simultaneous polishing of three materials: copper, dielectric (oxide), and barrier. Barrier is a very thin layer (Tan, Ti, etc.) that prevents the copper from diffusing into the dielectric. The goal in copper CMP is to remove the excess copper (also called overburden copper) and to polish the barrier on top of the dielectric regions isolating the adjacent interconnect lines. This is required to prevent electrical connection between adjacent interconnect lines. Owing to the heterogeneous nature of copper CMP, a specific set of process parameters as well as a consumable set are required to achieve the particular RR for each corresponding material [68]. Two major defects caused by copper CMP are pattern-dependent problems of metal dishing and dielectric erosion as shown in Figure 36.6. If the height of the copper in the trench is lower than the height of the neighboring dielectric, then dishing is positive otherwise it is negative. On the other Erosion Dishing Dielectric Pre-CMP dielectric level Copper FIGURE 36.6 Dishing and erosion. (From Tugbawa, T., Chip-Scale modeling of pattern dependencies in copper chemical–mechanical polishing processes, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 744 Finals Page 744 10-10-2008 #9 Handbook of Algorithms for Physical Design Automation Field region Recess Dielectric Field region Copper FIGURE 36.7 Definition of recess. (From Tugbawa, T., Chip-Scale modeling of pattern dependencies in copper chemical–mechanical polishing processes, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.) hand, dielectric erosion is always positive due to the loss of dielectric thickness during the CMP process. The sum of dishing and erosion gives the copper thickness loss (also known as the copper thinning) during CMP [68].∗ Another pattern-dependent defect occurring during copper planarization is recess. Recess of a copper interconnect line is equivalent to the dishing of that line. However, the recess of the dielectric within an array of interconnect lines is the difference between the dielectric height at a location within the array and the height of surrounding dielectric fields as shown in Figure 36.7 [68]. The goal in copper CMP is to remove the excess copper and the unwanted barrier layer. Ideally, this process should be fast without incurring extra dishing, erosion, or other defects. Owing to heterogeneous nature of copper CMP, different materials are polished simultaneously. Initially, only overburden copper is polished followed by the polishing of both copper and barrier film. Finally, copper, barrier, and dielectric are polished at the same time. As stated in Ref. [68], to model copper CMP process three stages of polish are identified: excess copper removal, barrier film removal, and overpolish stage, as shown in Figure 36.8. In the excess copper removal stage, the evolution of the Stage 1 Bulk copper removal Stage 2 Barrier removal Stage 3 Overpolish Oxide erosion Cu dishing FIGURE 36.8 Three intrinsic stages in copper CMP processes. (From Tugbawa, T., Chip-Scale modeling of pattern dependencies in copper chemical–mechanical polishing processes, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.) ∗ In the published literature, erosion is sometimes referenced to the height of a neighboring field dielectric region, and a separate field dielectric loss parameter is then specified. In Ref. [68], a single dielectric erosion term is used to represent dielectric loss. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 CMP Fill Synthesis: A Survey of Recent Studies Finals Page 745 10-10-2008 #10 745 copper thickness profile across the chip and the time it takes to remove the excess copper are of interest. The time to polish the overburden copper varies across the die depending on the pattern density at the location of interest. In the second stage, copper and barrier film are polished simultaneously. The time to clear the barrier film, as well as the dishing that results when barrier is removed at any location on the die, is of interest. Due to process variation and deposited copper thickness variation across the wafer and different pattern densities across the die, the RRs of the three materials (copper, barrier, and dielectric) are different. This difference in RRs results in different polish times across the wafer for each stage. For example, by the time the excess copper and barrier are cleared at a point on the die, they might have already been cleared at another point. Hence, some points on the die are overpolished. In copper CMP, overpolishing is defined as polishing beyond the time it takes to remove the overburden copper and barrier at any spatial location. During the overpolishing stage, the dielectric is eroded [68]. In addition, the dishing that might have started during the barrier clearing stage can worsen during overpolishing. This overpolishing is identified as the third intrinsic stage in the copper CMP process. The dishing and erosion that occur during this stage are of interest. In computing the amount of dishing during the overpolish stage, the dishing that occurs during the barrier clearing stage is used as an initial condition. It is important to note that the term overpolishing is used loosely in the CMP literature, and in the CMP industry [68].∗ 36.3.4 STI CMP MODELING Shallow trench isolation is the isolation technique of choice in CMOS technologies. In STI, trenches are etched in silicon substrate and filled with silicon dioxide to electrically separate active devices [31]. The previously used isolation technique, LOCOS (local oxidation of silicon), suffers from lateral growth that causes the isolation region to widen beyond the etched spaces. This lowers the integration density. It also complicates device fabrication and introduces device functionality problems such as high parasitic capacitances [47]. As described by Lee [36], the typical STI process flow initially involves growing a thin pad oxide, and then depositing a blanket nitride film on a raw silicon wafer. The isolation trenches are etched such that the desired trench depth (i.e., depth from silicon surface) is achieved. The CMP process is used to polish off the overburden dielectric down to the underlying nitride, where the nitride serves as a polishing stop layer. After CMP, the nitride layer is then removed via etch, resulting in active areas surrounded by field trenches. A typical STI process flow is shown in Figure 36.9. Lee [36] identifies two major phases in STI CMP process. The first phase is the polish of overburden oxide. The second phase is the overpolish into the nitride layer. The second phase is due to the different pattern densities across the die, for example, CMP pad contacts the nitride layer at different locations at different times. The first phase can be further broken down into two subphases. The first subphase happens between the start of the polish and before the CMP pad contacts the down areas (i.e., areas with lower height than their surroundings). The second subphase occurs from the time CMP pad contacts the down areas until the up area overburden oxide has been completely cleared to nitride. The first subphase has a homogeneous nature in that only one material is being polished at each moment. Reference [36] uses RR diagram to represent the polish of a single material. In this analysis, the assumption is that the initial starting point is a spatial location on the dielectric layer with a fixed step height. The feature densities for each point vary depending on the location on the die. Thus, any spatial location with a fixed effective pattern density can be expressed using a RR diagram. Figure 36.10 shows the RR diagram for phase one. For a significantly large step height, the CMP pad only contacts the up areas, and the down area RR is zero. This is the first subphase denoted as phase 1A as shown in the figure. The up areas polish at a patterned RR, K/ρ, as shown on the RR diagram. ∗ In the CMP industry, overpolishing means polishing beyond the endpoint time. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 746 Finals Page 746 10-10-2008 #11 Handbook of Algorithms for Physical Design Automation Silicon wafer Raw silicon wafer Deposit nitride/oxide stack Silicon wafer Nitride/pad oxide Typical deposition nitride 1500 Å T Etch isolation trenches Silicon wafer Typical trench depth 5000 Å (does not include nitride/oxide stack) SiO2 z0 Deposit dielectric (SiO2 oxide) Silicon wafer Typical deposition z0 = 9000 Å CMP to remove overburden oxide Silicon wafer Active area Field region Nitride removal Silicon wafer FIGURE 36.9 Typical STI process. (From Lee, B., Modeling for chemical–mechanical polishing for shallow trench isolation, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.) RR CMP pad Phase 1B Phase 1A Phase 1A K _ r Oxide Up area RR CMP pad K Down area RR 0 Phase 1B Oxide hc Step height (H ) Phase 1A indicates polish before the CMP pad contacts the down areas. Phase 1B indicates polish after down area has been initially contacted. FIGURE 36.10 RR diagrams for STI CMP polish (oxide overburden phase). (From Lee, B., Modeling for chemical–mechanical polishing for shallow trench isolation, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 747 10-10-2008 #12 747 CMP Fill Synthesis: A Survey of Recent Studies RR RR Slope KPnit Slope KPox P Nitride P Oxide FIGURE 36.11 RR versus pressure, for oxide and nitride. (From Lee, B., Modeling for chemical–mechanical polishing for shallow trench isolation, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.) As CMP process progresses, the step height reduces and eventually the polishing pad contacts the down areas. This is when the second subphase starts, denoted as phase 1B in the figure. The up and down RRs linearly approach each other until the step height is zero, after which the entire oxide film is polished at the blanket oxide RR K [36]. Owing to heterogeneous nature of the second STI CMP phase, a different removal diagram is used to express the polish of the two separate materials of silicon dioxide and silicon nitride. Figure 36.11 shows the two RR versus pressure curves for nitride and oxide. Assuming a Prestonian relationship, these are linear curves [36]. Dishing and erosion equations can be derived from the amount removal equations. These equations are more useful because it is the dishing and erosion phenomenon that is of most interest in STI CMP. The dishing and erosion equations are also more useful because they isolate key model parameters, making simpler equations from which to extract out model parameters. Dishing is simply the step height as a function of time and erosion can be computed as the amount of nitride removed. Therefore, dishing and erosion can be fully specified and predicted if the phase 1 and phase 2 STI CMP model parameters are known. These model parameters are characteristic of a given CMP process (tool, consumable set, etc.), and the model equations can be used to predict dishing and erosion on wafers patterned with arbitrary layouts that are subjected to a specific characterized CMP process [36]. In Section 36.4, density analysis methods are introduced. To asses the post-CMP effect, the pattern density parameter must be computed. 36.4 DENSITY ANALYSIS METHODS Traditionally, only foundries have performed the postprocessing needed to achieve pattern density uniformity using insertion “filling” or partial deletion “slotting” of features in the layout [26]. However, layout pattern density must be calculated before addressing the filling or slotting problem. Regions that are violating the lower and upper area density bounds are identified using density analysis methods. Kahng et al. [26] present three density analysis approaches with different time complexities all using the following density analysis problem formulation: Extremal-density window analysis. Given a fixed window size w and a set of k disjoint rectangles in an n × n layout region, find an extremal-density w × w window in the layout.∗ ∗ Borrowing the terminology from Ref. [26], an extremal-density window is a window with either maximum or minimum density over all the windows throughout the layout. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 748 Finals Page 748 10-10-2008 #13 Handbook of Algorithms for Physical Design Automation Tile Windows FIGURE 36.12 Layout is partitioned by r 2 (r = 4) fixed dissections into nrw × nrw tiles. Each w × w window (light gray) consists of r 2 tiles. A pair of windows from different dissections may overlap. (Kahng, A.B., Robins, G., Singh, A., and Zehikovsky, A., Proceedings of IEEE International Conference on VLSI Design, 1999.) 36.4.1 FIXED-DISSECTION REGIME To verify (or enforce) upper and lower density bounds for w × w windows, a very practical method is to check (or enforce) these constraints only for w × w windows of a fixed dissection of the layout into wr × wr tiles, that is, the set of windows having top-left corners at points (i · wr , j · wr ), for i, j = 0, 1, . . . , r( wn − 1), as shown in Figure 36.12. Here r is an integer divisor of w. To analyze all the eligible w × w windows takes a significant amount of time, while the analysis of fixed dissections can be done much faster. Simply an array of wn × wn counters will be associated with all the dissection windows, and then for each rectangle R the counters of windows intersecting R will be incremented by the area of intersection. In general, the above procedure must be repeated r 2 times to check all the (r · wn )2 windows [26]. 36.4.2 MULTILEVEL DENSITY ANALYSIS Even though the fixed dissection analysis can be performed quickly, it can underestimate the maximum floating-window density worst case.∗ Kahng et al. [28] propose a new multilevel density analysis approach that, as opposed to the techniques presented in Refs. [26,27], has the efficiency of the fixed dissection analysis without sacrificing the accuracy for the floating window worst-case analysis. The multilevel density analysis is based on the following simple observation. Observation. Given a fixed r-dissection, any arbitrary floating w × w window will contain some shrunk w(1 − 1/r) × w(1 − 1/r) window of the fixed r-dissection, and will be contained in some bloated w(1 + 1/r) × w(1 + 1/r) window of the fixed r-dissection as shown in Figure 36.13. The first implication of the above observation is that the floating window area can be upper bounded by the area of bloated windows, and lower bounded by the area of shrunk windows. A fixed ∗ In general, when all the eligible windows are being examined and filled, it is referred to as the floating window regime. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 749 10-10-2008 #14 749 CMP Fill Synthesis: A Survey of Recent Studies Fixed dissection window Floating window W Shrunk fixed dissection window Bloated fixed dissection window Tile FIGURE 36.13 Any floating w × w window W always contains a shrunk (r − 1) × (r − 1) window of a fixed r-dissection, and is always covered by a bloated (r + 1) × (r + 1) window of the fixed r-dissection. (Kahng, A. B., Robins, G., Singh, A., and Zehikovsky, A., Proceedings of IEEE Asia and South Pacific Design Automation Conference, 1999.) r-dissection regime can be recursively subdivided into smaller dissections until the number of tiles in each dissection is small. Then the floating density analysis can be applied without significant runtime complexity. In addition, the recursion can be terminated once the floating density analysis is within some user-defined criteria, say ε = 1 percent [28]. In this subsection, different density analysis approaches proposed by the authors of Refs. [26–28] have been presented. 36.5 CMP FILL SYNTHESIS METHODS Layout density problem includes two stages: density analysis and fill synthesis. Having presented the different approaches proposed for the density analysis stage, in this section the techniques used in fill synthesis will be reviewed. The first fill synthesis approach proposed by Ref. [26] was basically to first sort all the wires by rows, and within each row sort them by the coordinates of their leftmost starting points. Then, for each row, from left to right, metal fill would be placed in the space between the wires as shown in Figure 36.14. This simple method is based on scanline algorithm principles and is applicable to only wiring-type layouts. Reference [26] also proposes a simple technique for slotting. However, due to the reliability issues arising from slotting (i.e., change in current density due to change in wire cross section) it was not studied further, and the main focus of research is on fill insertion approaches. In the following four subsections, in Section 36.5.1, different density-driven problem formulations are presented. In Section 36.5.2, the model-based fill synthesis approach is introduced. In Section 36.5.3 the impact of CMP fill on circuit performance is investigated. And in Section 36.5.4, a new fill insertion method to be used in STI process is discussed. 36.5.1 DENSITY-DRIVEN FILL SYNTHESIS The following notation and definitions are used in defining the filling problem as described in Ref. [27]. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 750 Finals Page 750 10-10-2008 #15 Handbook of Algorithms for Physical Design Automation (a) (b) FIGURE 36.14 (a) Example of a wiring-type layout and (b) a corresponding fill solution. (Kahng, A. B., Robins, G., Singh, A., Wang, H., and Zelikovsky, A., Proceedings of ACM/IEEE International Symposium on Physical Design, 1998.) • Input is a layout consisting of rectangular geometries, with all sides having length as a multiple of c (minimum feature width, spacing). • n ≡ side of the layout region. If the layout region is the entire die, n might be about 50, 000·c. • w ≡ fixed window size. The window is the moving square area over which the layout density rule applies. • k ≡ layout complexity, number of input rectangles. • U ≡ area density upper bound, expressed as a real number 0 < U < 1. Each w × w region of the layout must contain total area of features ≤ U · w2 . • B ≡ buffer distance. Fill geometries cannot be introduced within distance B of any layout feature. • slack (W ) ≡ slack of a given w × w window W . Slack (W ) is the maximum amount of fill area that can be introduced into W . Using the above notation and definition the filling problem is stated as follows [27]: Filling problem. Given a design rule-correct layout geometry of k disjoint rectilinear rectangles in an n × n layout region, minimum feature size c, window size w < n, buffer distance B, and area (or perimeter) density lower bound L and upper bound U, add fill geometries to create a filled layout that satisfies the following conditions: 1. Circuit functionality and design rule-correctness are preserved. 2. No fill geometry is within distance B of any layout feature. 3. No fill is added into any window that has density ≥U in the original layout. 4. For any window that has density

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Handbook of algorithms for physical design automation part 77

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