Handbook of algorithms for physical design automation part 75.pdf (Sổ tay thuật toán)

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 722 Finals Page 722 24-9-2008 #29 Handbook of Algorithms for Physical Design Automation E E E x = ∆x x=0 H x = 2 ∆x H x = 1.5 ∆x E E E t = 0.5 ∆t x = 2.5 ∆x E H E t=0 x = 3 ∆x H x = 0.5 ∆x H E E H E t = ∆t t = 1.5 ∆t E t = 2 ∆t x=0 x = ∆0 x = 2 ∆x x = 3 ∆x FIGURE 35.29 Illustration of the time steps used in the computation of EM fields according to the FDTD Method. (Adapted from Taflove, A. and Hagness, S.C., Computational Electrodynamics: The Finite-Difference Time-Domain Method, Artech House, Boston, 2005. With permission.) properties of air, quartz, and chromium have been measured and can be found in Ref. [94], this tends to not be a practical drawback to its use. More critical is the fact that the grid must extend throughout the space to be simulated. If a large system such as an entire lens were to be simulated point by point, the amount of computation would be gigantic. Lens propagation is well described by the approximations described previously, in Section 35.2.2.2 and using the Hopkins method of Section 35.3.2. To use the more accurate results of the FDTD simulation where it matters, at the mask and more particularly at the patterned surface of the mask, a grid can be set up to only simulate the thin region at the quartz/chrome/air interface of the photomask, using fine grids (e.g., grid spacing of 5 nm for illumination wavelength λ = 193 nm). The scattering of the mask patterning structures can then be accurately computed locally using the FDTD method, and a replacement for the mask function, a new M (x, y), can be generated from the results at the bottom of the simulation window. This M (x, y) will have the amplitude and phase information as generated by the FDTD simulator, and the angular spectrum (e.g., Fourier transform) of this complex function can be used in the established equations. Another problem lies with the treatment of the boundary conditions. Normally, such a program would assume the edges are contiguous with another domain, periodically repeated from the grid under simulation. If this is actually the case on the photomask (e.g., with repeating cells or features), then this will be accurate, but to simulate isolated features, something must be done. The usual treatment here is to use perfectly matched layers (PMLs) [95] at the edges of the simulation domain that attenuate the incoming EM excitations. Ideally, there is no reflection at all from the PMLs, and analytically this is true. But with a discrete grid, some artificial reflection can occur, and at oblique angles, this can grow to be significant. Therefore, care must be taken when creating these black holes at the appropriate edges of the simulation regime to allow accurate simulation of local isolated layout patterns. If a suitable grid and boundary conditions are set up, the FDTD simulator produces correct results [96,97]. However, the computation time consumed to reach steady-state result, and to then Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Modeling and Computational Lithography Finals Page 723 24-9-2008 #30 723 infer a function that represents a complex effective mask transmission, makes this unmanageable as an in-line simulation tool for the simulations called for in full-chip RET. 35.3.3.2 RCWA and Waveguide Techniques Other techniques can also be used to provide a more rigorous technique for simulating the electromagnetic field without the computational intensity of the FDTD method. Rigorous coupled wave analysis (RCWA) [98] is a technique for modeling the light diffraction from gratings. The linearity of optics, as discussed above in Section 35.2, allows for the Fourier decomposition of an arbitrary pattern into a set of gratings, which can be computed individually and the final image reassembled. This technique is more commonly used for one-dimensional patterns [99]. The waveguide method (WGM) [100] assumes the object is periodic with rectangular sidewalls, and expands the fields in the object into the eigenmodes of a waveguide with a similar profile. Although these boundary conditions may be somewhat limited, they correspond to many real-world mask structures, such as certain phase-shifting masks [101], and when the boundary conditions are met, they can be several times faster than FDTD without a significant loss in accuracy [102]. 35.3.3.3 DDM An alternative approach to the in-line use of FDTD can be found in techniques such as the domain decomposition method (DDM) [103]. Here, a basis set of fundamental imaging components is determined. One possible set of basis elements is a collection of topographic edges of various dimensions, each one illuminated at particular angles and for each polarization (parallel and perpendicular). Another uses predetermined geometric regions. For each of the basis elements, the EM fields are presimulated using an accurate method, such as a FDTD simulator, and stored in a table for future use [104]. When a complex layout is encountered that requires simulation, the program decomposes the layout into a summation of the fundamental basis set elements, looks up and assembles the precomputed field contributions, and presents the resulting E fields. In this way, a fairly accurate simulation result for a complex topographic pattern can be presented without requiring a large area, time-consuming FDTD calculation. The DDM method is illustrated in Figure 35.30. For simulating topographic mask patterns, this has been quite successful using a basis set of chrome or quartz edges of various heights and lengths, illuminated with either parallel or perpendicular polarization. It relies, however, on the linearity of the EM system and the correct choice of a basis set for its success. If certain resonant phenomena are encountered, such as the excitation of surface plasmons at a metal/dielectric interface, [105–107] the basis set must be expanded to include the fundamental resonant structures, and the decomposition must be expanded to ensure that they are recognized. If nonlinear interactions occur, the technique will not work. 35.3.4 WAFER SIMULATION The image intensity I(x, y) that is produced corresponds to the image that would be formed in free space or air (the aerial image). Defocus, as discussed above, can be introduced as equivalent to a fourth-order aberration function. To model the effect of dose in the photoresist, the behavior of the image as it coupled into the photosensitive resist must be considered [108]. Photoresists are engineered to be very high contrast materials. This means that, once the exposure dose has exceeded a certain threshold, the desired reaction (either the breaking of bonds, or the formation of crosslinks) occurs rapidly and thoroughly [22]. For this reason, an image can be evaluated for regions in which the intensity exceeds the threshold versus those where intensity does not exceed a threshold, and the final pattern defined appropriately. The simplest approach is to determine Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 724 Finals Page 724 24-9-2008 #31 Handbook of Algorithms for Physical Design Automation Opaque T=1, φ = 0° T=1, φ = 180° FIGURE 35.30 Illustration of the DDM (Adapted Adam, K. and Neureuther, A., Proc. SPIE, 4691, 107, 2002. With permission.) a single threshold value, and apply that universally. This is called a constant threshold model for aerial image evaluation [41]. For some estimations, this works well, but results can vary with individual resists. Some modern resists for use with deep-UV exposure resists with chemical amplification operate with the creation of a catalyst through photoexposure. This catalyst then migrates through the polymer matrix, breaking bonds [22]. Depending on the density of the photocatalysts, the delivered dose can produce different effects in different regions. One can, as above, use a first-principles method to precompute resist profiles for a basis set of structures. In this case, the actual 3D intensity profile within the resist is computed, using all the reflections at the front and back surfaces that may cause interference within the layers [109]. The refractive indices of the resist and various coating layers are needed, and their change as exposure takes place (bleaching) must also be computed. The generation of photoactive compounds and their diffusion during postexposure baking can be simulated kinetically [110], and finally, the removal of material through the development process can also be modeled [111]. These photoexposure and development processes, however, are threshold-based processes. The ability to find a suitable set of basis structures that would allow a look-up table of resist results to be assembled into an image, analogous to DDM, would require a very large look-up table. Instead, it has been observed that the basic characteristics of resist image formation can be inferred by calibrating the actual formation of an image edge to the local aerial image parameters, such as local image maximum intensity (Imax ), intensity slope, etc. In a technique pioneered by Cobb [112], the variable threshold resist (VTR) method [41,112,113], creates a table of values relating image parameters (e.g., Imax , slope) and then determines the local threshold as a function of these imaging parameters. This is illustrated in Figure 35.31 and Figure 35.32. Other, more complicated functions have been derived for evaluating the relationship between printed (and even etched) image and the parameters in the image. These optimizations can be level specific, and often require extensive calibration. Their use for memory ICs, which are manufactured in great volumes, provide the best return on the investment in this calibration [114]. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 725 24-9-2008 #32 725 Modeling and Computational Lithography Intensity lmax 1.0 T = f (lmax m) 0.5 m x FIGURE 35.31 Intensity profile through a simulation cutline. (Adapted from Cobb, N.B., Fast optical and process proximity correction algorithms for integrated circuit manufacturing, Ph.D. Dissertation, University of California, Berkeley, California, 1998; Cobb, N.B., Zakhor, A., and Miloslavsky, E., Optical Microlithography IX, Proceedings of SPIE, 2726, 208, 1996. With permission.) Threshold empirical data points Threshold surface fit 0.6 0.6 0.4 0.4 0.2 0 0.6 0.2 3.5 0.7 3 0.8 2.5 0.9 Imax (a) 1 0 0.4 2 1.1 1.5 Slope (b) 3.5 3 0.6 2.5 0.8 1 Imax 2 1.2 1.5 Slope FIGURE 35.32 VTR model. (a) Empirical threshold values determined from linewidth measurements, and (b) a model surface that fits the empirical data. (Reproduced from Cobb, N.B., Fast optical and process proximity correction algorithms for integrated circuit manufacturing, Ph.D. Dissertation, University of California, Berkeley, California, 1998; Cobb, N.B., Zakhor, A., and Miloslavsky, E., Optical Microlithography IX, Proceedings of SPIE, 2726, 208, 1996. With permission.) The calibration of these functions requires that a test pattern of representative features be prepared in advance and printed using the resist process in question [41,115]. Such a test pattern is illustrated in Figure 35.33. Wafer results are then measured for each of the structures, and the result compared with a aerial image simulation of the image placement and the values for the imaging parameters. From the empirical calibration of the change in line placement with image parameters, the variable threshold values can be determined. This technique, once the test pattern calibration data has been gathered, has proven to be a very effective and fast way to generate the simulation results needed to generate EPEs and remains the fundamental methodology for most of the OPC computations in use today. 35.4 EDA RESULTS We have shown how simulation results can be generated, and seen one case of how the use of a call to a simulator by an RET tool is used to dictate the motion of edges for process compensation. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 726 Finals Page 726 24-9-2008 #33 Handbook of Algorithms for Physical Design Automation FIGURE 35.33 Example of the layout of a test pattern used for creating empirical OPC models. (Courtesy Mentor Graphics.) This involves the simple use of a single simulation per site, or, in more recent implementations, the comparison of a layout and a contour. There are other applications that involve more sophisticated simulations. 35.4.1 PROCESS WINDOWS For lithographers, a typical test of a lithographic process is the focus–exposure matrix. Often called a Bossung plot, after the author of original paper proposing the technique, [116] or sometimes an ED-tree (for exposure–dose tree) [117], they are generated by making an array of exposures with a stepper, systematically changing focus and exposure dose. The resulting feature of interest is measured for each setting to form a matrix, allowing the range of settings for which the feature dimension (commonly called a CD, for critical dimension) is within a preset tolerance to be determined. The region over which acceptable feature deviation is achieved is called the process window. An example of a process window is illustrated in Figure 35.34 [60]. Typically, the acceptable region is the nominal dimension ±10 percent. Process windows are extremely useful tools for the evaluation of, for example, a novel RET approach [60,118]. Improving the process window with the addition of assist features or by using a different illuminator design is a standard procedure. The number of simulations that must be run to accurately estimate the behavior through focus and dose can vary, and dynamic adaptation of simulation settings can lead to more computationally efficient estimations without a significant loss in accuracy [119]. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 727 24-9-2008 #34 727 Modeling and Computational Lithography CD (nm) 800 700 160.0 mJ/cm22 180.0 mJ/cm2 200.0 mJ/cm2 220.0 mJ/cm2 240.0 mJ/cm2 260.0 mJ/cm2 280.0 mJ/cm2 300.0 mJ/cm2 320.0 mJ/cm Linewidth (nm) 600 500 400 300 200 100 0 Exposure energy (mJ/cm2) 360. (b) −1.5 0.20 µm −1.0 0.0 −0.5 Focus (µm) 0.30 µm 280. 240. 0.40 µm 200. 0.50 µm 160. −1.40 −.96 −.52 −.08 Focus (µm) .36 .80 CD SA RL 240 0.20 µm 320. 0.5 Exposure energy (mJ/cm2) (a) 220 200 180 160 −1.0 (c) −0.5 0.0 Focus (µm) 0.5 FIGURE 35.34 Determination of a process window. (a) Linewidth data as a function of defocus are plotted for various exposure doses. (b) Replotting of the data from (a) showing contours of constant linewidth and (c) determination of process conditions where the linewidth is within specification, forming a process window. (Reproduced from Mack, C., Design, Process Integration and Characterization for Microelectronics, Proceedings of SPIE, 4692, 454, 2002. With permission.) Other, more complicated functions have been derived for evaluating the relationship between printed (and even etched) image and the parameters in the image. One example from a recent paper is shown in Figure 35.35 [120]. Sometimes, because resists 100 nm thick are therefore out of focus by 100 nm at the top or bottom, additional image metrics incorporating computation of defocused images can also be considered. Process window OPC is an area of increasing sophistication for modeling and calibration for OPC applications. 35.4.2 MEEF Another use for simulation is the evaluation of the change in the image that occurs when a feature on a photomask is not accurately fabricated. The change in printed feature for a small change in the original photomask dimension is called the mask error enhancement factor (MEEF) [121,122]: MEEF = M CDwafer CDmask where M (not to be confused with M(x, y)) is the mask magnification factor (typically M = 4 for modern steppers). For large features using normal lithography, MEEF is typically 1. For smaller features, dimensions are eventually reached where these no longer print at all, as shown in Figure 35.36a. In these cases, the change in printed feature varies dramatically with the change in mask dimension, and MEEF is very large, as illustrated in Figure 35.36b [123,124]. The use of RET can be evaluated here not only by the improvement of the process window but also by the impact on MEEF [125]. For some choices of RET, this can be very advantageous. For Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 728 Finals Page 728 24-9-2008 #35 Handbook of Algorithms for Physical Design Automation 4 3 Factor 2 1 0 −1 −2 0.2 1.2 0.15 0.1 0.8 0.6 0.05 Imin 1 0.4 0 0.2 Imax FIGURE 35.35 Contemporary illustration of the extension of the model fitting routines as illustrated in Figure 35.32, but now considering process windows. (Reproduced from Shang, S., Granik, Y., Cobb, N., Maurer, W., Cui, Y., Liebmann, L., Oberschmidt, J., Singh, R., Vampatella, B., Optical Microlithography XVI, Proceedings of SPIE, 5040, 431, 2003. With permission.) 5 Reticle CD/4 Resist CD 4 300 Resist MEEF MEEF Measured CD (nm) 400 200 100 0 3 2 1 0 100 200 300 Wafer target CD (nm) 400 0 0 100 200 300 400 Wafer target CD (nm) FIGURE 35.36 Measured CD versus desired CD for an isolated line (left). CD stands for critical dimension, a common metrology term to designate a linewidth. For small features, the process completely fails. Corresponding MEEF result (right). As the process fails, the MEEF clearly increases dramatically. (Adapted from Schellenberg, F.M., Boksha, V., Cobb, N., Lai, J.C., Chen, C.H., and Mack, C., Optical Microlithography XII, Proceedings of SPIE, 3679, 261, 1999. With permission.) example, the image of a phase edge formed by a phase shifting mask, the dark fringe occurs no matter what the dimension of the photomask, and the MEEF approaches zero for this technique. This is illustrated in Figure 35.37 [60,126]. 35.4.3 PV-BANDS Simulation can be used to also evaluate the typical extremes of a process, and then used to generate contours representing the placement of these edges on the wafer under these extreme conditions. These contours can be converted to a sequence of vertices and stored in the layout database as Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 729 24-9-2008 #36 729 250 5 200 4 150 3 MEEF MEEF Wafer CD (nm) Modeling and Computational Lithography 100 50 2 1 0 0 50 100 150 200 250 Measured reticle phase separation/4 (nm) 0 0 50 100 150 200 Wafer target CD (nm) 250 FIGURE 35.37 Measured CD versus desired CD for an isolated line fabricated using a phase-shifting mask (left). For small features, the linewidth converges to the fundamental limit formed by the narrow, dark interference fringe. The corresponding MEEF result (right). (Adapted from Schellenberg, F.M., Toublan, O., Cobb, N., Sahonria, E., Hughes, G., MacDonald, S., and West, C., Proc. SPIE, 4000, 1062, 2000. With permission.) PV-bands (process variation bands) [127]. These are illustrated in Figure 35.38. These are similar to the contours generated by other image simulation techniques, and can be used in DRC and other checking operations to verify that the layout, even if distorted by manufacturing processes, can still pass. In the past, the generation of PV-bands throughout an entire layout was too computationally intensive to be practical. Now, with the computing power typically brought to bear to generate OPC layouts, computing PV-bands for every feature in the layout becomes possible, and if the hierarchy of the original layout can be maintained for the layouts rendered as PV-bands, even practical. Maximum Variability region Printability Non-printability Minimum FIGURE 35.38 Illustration of a layout polygon and its corresponding process variation (PV)-bands. (Reproduced from Robles, J.A.T., Integrated circuit layout design methodology for deep sub-wavelength processes, Ph.D. Dissertation, OGI School of Science and Engineering, Beaverton, Oregon, 2005. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 730 Finals Page 730 24-9-2008 #37 Handbook of Algorithms for Physical Design Automation FIGURE 35.39 Portion of a layout where the PV-bands have flagged a violation (left), and (upper right) the corresponding simulated layout and (lower right) the printed wafer behavior. (After Robles, J.A.T., Integrated circuit layout design methodology for deep sub-wavelength processes, Ph.D. Dissertation, OGI School of Science and Engineering, Beaverton, Oregon, 2005. With permission.) 9.78 Signal arrival time (ns) Dose 9.76 0.9 0.95 1 1.05 1.1 1.15 1.2 9.74 9.72 9.7 TT 9.68 9.66 9.78 −250 −200−150−100 −50 0 50 100 150 200 250 300 Defocus (nm) Signal arrival time (ns) Dose 9.76 9.74 9.72 9.7 9.68 9.66 TT 0.9 0.95 1 1.05 1.1 1.15 1.2 −250 −200−150−100 −50 0 50 100 150 200 250 300 Defocus (nm) FIGURE 35.40 Standard layout (upper), with the corresponding timing information as a function of lithographic defocus. The layout (lower), modified slightly to be more uniform and to remove the possible sources of variation highlighted by the PV-bands, along with the corresponding improvement in timing with variation in defocus. (After Robles, J.A.T., Integrated circuit layout design methodology for deep sub-wavelength processes, Ph.D. Dissertation, OGI School of Science and Engineering, Beaverton, Oregon, 2005. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Modeling and Computational Lithography Finals Page 731 24-9-2008 #38 731 35.4.4 EXTRACTION The generation of data layers corresponding to PV-Bands opens up the possibility of linking the PV-band layout not only to a DRC tool but also to an extraction tool. By using the PV band for a circuit instead of the nominal layout (or a simulated result at perfect focus and exposure) in an extraction tool, the effect of process variations on electrical properties can now be determined [128]. An example of this is shown in Figures 35.39 and 35.40. Here, simulated results for a cell have been generated with PV-bands under various settings, and the timing behavior of the circuit determined using an extraction tool. Rather than predict the imaging fidelity using process windows (which may or may not correlate with electrically meaningful performance), this link to extraction and SPICE modeling can allow lithographic modeling to predict the electrical performance of a circuit, and its response to variation in optical parameters. 35.5 CONCLUSION This chapter has attempted to present an overview of the interaction of an EDA layout flow using process modeling, and given details on the specific example of lithographic process modeling. Maxwell’s equations and the Fourier transforms used in optics have been well known and characterized for over a century, and this has lead to a very mature algorithmic environment for introducing these computations for all features in an EDA layout. There are other processes that can be modeled, such as (CMP) [11–13] and plasma etching [129]. The results of these models have direct consequences for the layout and design, for example, in the domain of density dummy fill patterns inserted into a layout to improve the CMP uniformity. However, these are not as well understood as lithography processes, and are often based purely on empirical characterization. The utility of these models, however, will follow the same principle as for the flow outlined in Figure 35.1. As computing power continues to grow and become even more inexpensive, the seamless insertion of large computational modeling modules into EDA flows, as has already been done for RET, is expected to grow and make the accounting of process variability a routine part of the design process. REFERENCES 1. L. Scheffer, L. Lavagno, and G. Martin, Electronic Design Automation for Integrated Circuits Handbook, CRC Press, Boca Raton, FL, 2006. 2. Handbook of Semiconductor Manufacturing Technology, Y. Nishi and R. Doering, Eds., Marcel Dekker, New York, 2000. 3. S. Wolf, Microchip Manufacturing, Lattice Press, Sunset Beach, CA, 2004. 4. S. Wolf, Silicon Processing for the VLSI Era, Vols. 1–4, Lattice Press, Sunset Beach, CA, 2002. 5. R. Dutton and Z. Yu, Technology CAD—Computer Simulation of IC Processes and Devices, Kluwer Academic Publishers, Dordrecht, Netherlands, 1993. 6. F.M. Schellenberg, Design for manufacturing in the semiconductor industry: The litho/design workshops, in Proceedings of the 12th International Conference on VLSI Design, R. Sipple, Ed., IEEE Computer Society Press, Los Alamitos, CA, 1999, pp. 111–119. 7. GDSII Stream Format Manual, Release 6.0, Documentation No. B97E060, Cadence Design Systems, Inc./Calma, San Jose, CA, Feb. 1987. 8. SEMI P39-0304E2-OASIS—Open Artwork System Interchange Standard, available at. www.semi.org/. 9. A. Vladimirescu, The SPICE Book, John Wiley, New York, 1994; and G. Roberts and A. Sedra, SPICE, Oxford University Press, Oxford, United Kingdom, 1997. 10. A.B. Kahng, G. Robins, A. Singh, and A. Zelikovsky, Filling algorithms and analyses for layout density control, IEEE Transactions on Computer-Aided Design, 18(4), 445–462, 1999. 11. Y. Chen, A.B. Kahng, G. Robins, and A. Zelikovsky, Area fill synthesis for uniform layout density, IEEE Transactions on Computer-Aided Design, 21(10), 1132–1147, 2002.

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