Handbook of algorithms for physical design automation part 60.pdf (Sổ tay thuật toán)

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 572 Finals Page 572 30-9-2008 #5 Handbook of Algorithms for Physical Design Automation Algorithm: Buffered _Path(G, B, s, t) Input: Routing graph G = (V, E ), Buffer library B Source node s ∈ V and sink node t ∈ V Output: Buffered path labeling m 1. Q ← {(C, 0, 0, t)} 2. while Q = ∅ do 3. (c, d, m, u) ← extract_min(Q ) 4. if c = 0, return m 5. if u = s, push (0, d + Rd · c, m, s) into Q and prune continue 6. for each (u, v ) ∈ E do d ← d + R(u, v ) · (c + C (u, v )/2) push (c + C (u, v ), d , m, v ) into Q and prune 7. if p(u) = 1 and m (u) = 0 8. for each b ∈ B do d ← d + R (b ) · c + K (b ) m (u ) = b push (C (b ), d , m, u) into Q and prune FIGURE 28.4 Pseudocode of the dynamic programming-based buffered path algorithm. with m(v) = b. If a solution reaches the source node as (c, d, m, s), the driver is added by updating the solution as (0, d + Rd · c, m, s). When a solution with the driver is at the top of the Q, it is the minimum delay solution. The pseudocode of this algorithm is given in Figure 28.4. Please note that pruning is performed in many steps to remove inferior solutions so that the runtime can be improved. The complexity of this algorithm is O(|BV |(|E| + |BV |) log |BV |) [1]. 28.3.2 GRAPH-BASED APPROACH The graph-based approaches [3,4] first transform the routing graph G = (V , E) into a buffer graph GB = (VB , EB ) and then obtain the minimum delay buffered path by the Dijkstra’s shortest path algorithm. The node set VB of the buffer graph is composed of the source node, sink nodes, and a set of buffer nodes. A buffer node always has a buffer inserted and therefore it has to be out of any buffer blockage. An edge e ∈ EB is usually directed from the source or a buffer node to a buffer node or the sink node (Figure 28.5a). There is a delay associated with each edge. If the Elmore delay model is employed, the delay d(u, v) for edge (u, v) is equal to R(u)·(C(u, v)+C(v))+R(u, v)·(C(u, v)/2+C(v)) where Source Buffer Buffer Buffer Buffer u Sink (a) FIGURE 28.5 Buffer graph. (b) (c) b1 b2 v b1 b2 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 Finals Page 573 30-9-2008 #6 573 Buffering in the Layout Environment R(u) is the driving resistance at u, R(u, v) is the edge resistance, C(u, v) is the edge capacitance, and C(v) is the input capacitance at v. Unlike the routing graph introduced in Section 28.3.1, the two end nodes of an edge in the buffer graph do not have to be geometrical neighbors. An example of buffer graph is shown in Figure 28.5b. If the edge delay is treated as edge weight, the minimum buffered path is equivalent to the shortest path on this buffer graph. Thus, the optimal solution can be found easily by applying Dijkstra’s shortest path algorithm on the buffer graph. The graph-based approach can be easily extended to handle multiple buffer types and wire sizing. If there are k buffer types, each buffer node is split into k copies each of which corresponds to one type. Edges are inserted among these copies of nodes. In Figure 28.5c, an example of two buffer types is shown. Similarly, if there are multiple wire widths, the edge weight is chosen as the minimum edge delay among all options of wire widths [4]. Then, discrete wire sizing is naturally handled in the same framework. Besides minimizing the path delay, the problem can be formulated [3] as maximizing delay −d(p) reduction to cost ratio Drefg(p) where Dref is a reference delay, d(p) is the path delay of path p, and g(p) is the path cost. The path cost is simply the total edge cost along the path. The edge cost can be defined in many different ways. For example, it can be the summation of wire capacitance and buffer/sink capacitance of its downstream end. Let Rmax represent the maximum ratio can be obtained. Then Dref − d(e) e∈p Rmax = g(e) e∈p or equivalently Rmax e∈p g(e) + d(e) = Dref e∈p Delay If the weight of each edge e is set to Rmax g(e) + d(e), the total path weight is equal to Dref . The value of Rmax can be obtained by probing different values in a binary search manner. For a guess I of Rmax , the shortest path weight is obtained when each edge weight is labeled as I · g(e) + d(e). If the result is greater (smaller) than Dref , the value of I is increased (decreased). When the path weight is sufficiently close to Dref , its corresponding value of I can be treated as Rmax . As the value of Dref decreases, the cost of the corresponding maximum ratio path increases [3]. There exists a Dref for which a (g, d) path is optimal if and only if (g, d) lies on the lower convex hull of the trade-off curve between cost g and delay d [3]. The solutions on a lower convex hull is illustrated in Figure 28.6. Cost FIGURE 28.6 All circles represent the set of noninferior solutions. The dark circles lie on the lower convex hull. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 574 Finals Page 574 30-9-2008 #7 Handbook of Algorithms for Physical Design Automation 28.4 BUFFERED TREE WITH BLOCKAGE AVOIDANCE The situation of multipin nets is much more difficult than that of two-pin nets as Steiner tree construction itself is a hard problem. There are two categories of approaches: (1) constructing a Steiner tree regardless of buffer blockages and then adjusting the tree to avoid blockages and (2) simultaneous Steiner tree construction and buffer insertion with awareness of blockages. 28.4.1 TREE ADJUSTMENT TECHNIQUE As a relatively easy method, one can start with a Steiner tree regardless of blockages and modify the tree to avoid blockages [5]. This can be performed in a fashion similar to the rip-up and reroute in congestion avoidance of global routing. In other words, if a path in the tree has large overlap with blockages, it is ripped up and reconnected back to the tree with a path having less overlap with blockages. This is illustrated in Figure 28.7. In each iteration, the path with the largest overlap with blockages is chosen for rerouting. The reconnection procedure is done by running Dijkstra’s algorithm on the extended Hanan grid graph indicated by the dashed lines in Figure 28.7. In this graph, the weight of an edge is its length if it does not overlap with any blockage. If an edge overlaps with a blockage, its weight is its length times α, where α > 1 is a penalty coefficient. The value of α decides the trade-off between blockage avoidance and wire increase due to detour. After the tree modification, the chance of feasible buffering solutions is increased. Because the rerouting has no knowledge if buffers are needed on a path, it may cause some unnecessary wire detours. Another technique is to integrate the tree adjustment with buffer insertion [6] so that wire detour is incurred only when it is necessary for buffer insertion. The classic van Ginneken’s buffer insertion algorithm [7] propagates a set of candidate solutions from the sink nodes toward the source and picks the optimal one at the source. The adaptive tree adjustment technique generates a candidate solution with an alternative Steiner node if the original Steiner node is inside a blockage. This adjustment is a part of a candidate solution, which is propagated toward the source. This adjustment is adopted only when its corresponding candidate solution is selected at the source. In other words, the tree adjustment is made according to the need of buffer insertion. In Figure 28.8, an example is depicted to demonstrate this technique. 28.4.2 SIMULTANEOUS TREE CONSTRUCTION AND BUFFER INSERTION The problem of whether or not to avoid a blockage and how to avoid can be solved by simultaneously constructing Steiner tree and inserting buffers [8–10]. Compared to the tree adjustment techniques, the simultaneous approach can lead to improved solution quality with increased computation cost. There are two major methods of the simultaneous approach: dynamic programming [8] and graph based [9]. a a s c s a s d b (a) b b (b) FIGURE 28.7 Rip-up and reroute to avoid blockages. d (c) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 Finals Page 575 30-9-2008 #8 575 Buffering in the Layout Environment Source Alternative Steiner point Buffer blockage vl vp v⬘ vl v vp v Subtree Subtree vr vr (a) (b) FIGURE 28.8 For a Steiner node v within a buffer blockage as in (a), an alternative Steiner node v is generated as another candidate solution allowing buffer insertion as in (b). (From Figure 2 of Hu, J., Alpert, C. J., Quay, S. T., and Gandham, G., IEEE Trans. Comput. Aided Des. Integrated Circuits Syst., 22, 494, 2003. With permission.) 28.4.2.1 Dynamic Programming-Based Method The dynamic programming-based method, called RMP (recursive merging and pruning) is performed on a routing graph like Figure 28.3. Similar to the fast path algorithm [1], it propagates candidate solutions over the graph. The difference is that RMP considers merging solutions to form subtrees. Each candidate solution is characterized by (c, q, RE, buf, v) where c is the downstream load capacitance, q is the required arrival time, RE is the reachable sink set in the subtree, and v is the root of the subtree. The label buf = 1 if a buffer is inserted at the node, buf = 0 otherwise. The candidate solutions are maintained in a priority queue with the maximum-q solution on the top. When merging two solutions at a node, one need to ensure that the reachable sink sets of the two solutions are disjoint. If a sink appears in both of the solutions, then the merging implies nontree topology. If solution (c1, q1 , RE1 , buf1, v) and (c2, q2 , RE2 , buf2, v) are merged, the merged solution is (c1 + c2 , min(q1 , q2 ), RE1 ∪ RE2 , 0, v). For solutions at the same node of the routing graph, a pruning can be performed among them if they all have the same reachable sink set. The pruning is same as that described in Section 28.3.1. The RMP algorithm can reach the optimal solution in exponential time. To reduce runtime, one can perform an aggressive pruning that keeps only the minimum-c solution for each reachable sink set [8]. This technique can improve runtime significantly with very limited sacrifice on solution quality. 28.4.2.2 Graph-Based Technique The graph-based method [9] starts with constructing a look-up table storing precomputed tree components. Then, an abstraction graph is generated with each edge corresponding a tree component that can be obtained from the look-up table. The buffered tree with minimized maximum sink delay is obtained by applying Dijkstra’s shortest path algorithm on the abstraction graph. The tree components include • Wire path: a path connecting two nodes in the routing graph by properly sized wires but no buffers are between them • Buffered path: a path connecting two nodes in the routing graph with buffers inserted between • Buffer combination: a tree component connecting three or more nodes in the routing graph without internal buffers • BC-subtree: a subtree rooted with a buffer combination Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 576 Finals Page 576 30-9-2008 #9 Handbook of Algorithms for Physical Design Automation Buffered path Wire path BC-subtree Buffer combination FIGURE 28.9 Notations for graph-based simultaneous tree construction and buffer insertion. (From Figure 4 of Tang, X., Tian, R., Xiang, H., and Wong, D. F., Proc. IEEE/ACM Inter. Con. Comput. Aided Des., pages 51 and 52, 2001. With permission.) These components are illustrated in Figure 28.9. The minimum delay buffered path can be obtained by the method in Refs. [3,4], which is introduced in Section 28.3.2. A buffer combination can be treated as an unbuffered Steiner tree. Its delay is specified as the maximum root-leaf delay. If the number of nodes is restricted, the minimum delay buffer combination can be obtained by enumeration. Both the minimum delay buffered paths and the minimum delay buffer combinations are saved in look-up tables for future query. On the basis of buffer combinations, BC-subtrees, which are subtrees rooted at a buffer combination, can be constructed to drive a set of sinks. A few examples of BC-subtrees are shown in Figure 28.10. A buffered Steiner tree (or subtree) is composed of a set of buffered paths and BC-subtrees in general. Therefore, a general problem is how to construct a buffered tree (or subtree) that drives a certain set of sinks = {s1 , s2 , . . .}. This is achieved by using an abstraction graph G illustrated in Figure 28.11. This graph consists of a source node, which is the set of sinks , and a set of possible buffer nodes. An edge (, v) represents the optimal BC-subtree rooted at v, and its weight is the maximum delay of the BC-tree. The edge (u, v), where u, v ∈ , represents the optimal buffered path between u and v, which can be found in the look-up table. Then, the shortest path from to each other node v corresponds to the optimal subtree connecting to the sink set . The algorithm proceeds to creates subtrees by increasingly considering more sinks. This algorithm can minimize the maximum source–sink delay, but not the timing slack. In fact, it can reach the optimal solution in exponential time. v s1 s2 s1 v v v s2 s1 s2 s1 s2 FIGURE 28.10 Example of different BC-subtrees. (From Figure 8 of Tang, X., Tian, R., Xiang, H., and Wong, D. F., Proc. IEEE/ACM Inter. Con. Comput. Aided Des., pages 51 and 52, 2001. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 Finals Page 577 30-9-2008 #10 577 Buffering in the Layout Environment s1 s1 s2 s2 FIGURE 28.11 Graph for generating optimal subtree. (From Figure 9 of Tang, X., Tian, R., Xiang, H., and Wong, D. F., Proc. IEEE/ACM Inter. Con. Comput. Aided Des., pages 51 and 52, 2001. With permission.) 28.5 LAYOUT ENVIRONMENT AWARE BUFFERED STEINER TREE The previous sections presented different algorithms for buffer insertion and buffered tree construction avoiding buffer placement blockages. Practically, it is essential that buffer insertion algorithms consider layout environment such as the placement and routing congestion, which obviously leads to a more complicated problem. In this section, we start with the congestion assessment and then introduce several related algorithms. 28.5.1 MEASUREMENT OF PLACEMENT AND ROUTING CONGESTION To evaluate the placement and routing congestion of a buffered net, a tile graph is usually used to capture the congestion information and at the same time reduce the problem complexity. The tile graph is represented as G = (VG , EG ) such that VG = {g1 , g2 , . . .} is a set of tiles and EG is a set of boundaries each (gi , gj ) of which is between two adjacent tiles gi and gj . An example of the tile graph is shown in Figure 28.12. If a tile gi ∈ VG has an area of A(gi ) and its area occupied by placed cells gi FIGURE 28.12 Example of tile graph. gj Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 578 Finals Page 578 30-9-2008 #11 Handbook of Algorithms for Physical Design Automation a(gi ) are a(gi ), the placement density is defined as d(gi ) = A(g . Let W (gi , gj ) be the maximum number i) of wire tracks that can be routed across the tile boundary (gi , gj ) and w(gi , gj ) be the number of used w(g ,g ) tracks crossing (gi , gj ). Similarly, the boundary density is d(gi , gj ) = W(gi ,gj ) . To increase the penalty i j of using a congested tile (similarly for a tile boundary), using square cost (i.e., d(gi )2 ) ensures that the cost increases more rapidly as a tile is closer to becoming full. For example, the cost of using two tiles with densities of 0.1 and 0.9 is 0.82, while the cost of using two tiles with densities of 0.5 is 0.5. When considering both the placement and routing congestion cost for a net, the total cost incurred can be a linear expression of squares of both the tile densities and boundary densities. 28.5.2 PLATE-BASED TREE ADJUSTMENT When we consider both placement and routing congestions at the same time, applying simultaneous Steiner tree construction and buffer insertion seems to be computationally prohibitive for practical circuit designs. In the following, sequential approaches [11,12] are introduced to solve the problems. A good way to handle the placement and routing congestion is through the following four stages: (1) timing-driven Steiner tree construction, (2) plate-based adjustment for congestion mitigation, (3) local blockage avoidance (refer to Section 28.2.1), and (4) van Ginneken style buffer insertion. Because stages 1, 3, and 4 have been described in previous sections, the rest of the discussion focuses on the stage of plate-based tree adjustment. 28.5.2.1 Dynamic Programming-Based Adjustment The basic idea for the plate-based adjustment [13] is to perform a simplified simultaneous buffer insertion and local tree adjustment so that the Steiner nodes and wiring paths can be moved to less congested regions without significant disturbance on the timing performance obtained in stage 1. The plate-based adjustment traverses the given Steiner topology in a bottom-up fashion by the dynamic programming algorithm. During this process, Steiner nodes and wiring paths may be adjusted together with buffer insertion to generate multiple candidate solutions. We only use buffer insertion to estimate the placement congestion of the buffered tree and to guide the tree adjustment. Hence, the output of this stage is still an unbuffered net, only with changes in the Steiner tree routing. Besides, because buffer insertion is merely a mean of placement congestion estimation, a single typical buffer type can be used to simplify the calculation, while the Elmore delay model can be used for interconnect and a switch level RC gate delay model is adopted. For a Steiner node vi which is located in a tile gk , a plate P(vi ) for vi is a set of tiles in the neighborhood of gk including gk itself. During the plate-based adjustment, we confine the location change for each Steiner node within its corresponding plate. If vi is a sink or the source node we set P(vi ) = {gk }. The shaded box in Figure 28.13a gives an example of the plate corresponding to Steiner node v4 . The plate indicates any of the possible locations which the Steiner node may be moved to. The search for alternative wiring paths is limited to the minimum bounding box covering the plates of two end nodes. In Figure 28.13, such bounding boxes are indicated by the thickened dashed lines. Therefore, the size of plates define the search range for both Steiner nodes and wiring paths. As a result, the size of the plate controls the quality of solution/runtime trade-off desired by the user. With different plate sizes, we can obtain the ability to modify the topology to move Steiner points into low-congestion regions while also capping the runtime penalty. An example of how a new Steiner topology might be constructed from an existing topology is demonstrated in Figure 28.13a through c. It is suggested in Ref. [14] that buffer insertion can be performed in a simple nontiming-driven way by following a rule of thumb: the maximal interval between two neighboring buffers is no greater than certain upper bound. Similarly, we restrict the maximum load capacitance U a buffer/driver may Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 Finals Page 579 30-9-2008 #12 579 Buffering in the Layout Environment Source Source v1 v1 v5 v4 v1 v5 v4 v3 v2 (a) v4 v3 v2 (b) v5 v3 v2 (c) FIGURE 28.13 (a) Candidate solutions are generated from v2 and v3 and propagated to every tile, which is shaded, in the plate for v4 . Solution search is limited to the bounding boxes indicated by the thickened dashed lines. (b) Solutions from v1 and every tile in the plate for v4 are propagated to the plate for v5 . (c) Solutions from plate of v5 are propagated to the source and the thin solid lines indicate one of the alternative trees that may result from this process. (From figure 3 of Alpert, C. J., Gandham, G., Mrkic, M., Hu, J., Quay, S. T., and Sze, C. -N., IEEE Trans. Comput. Aided Des. Integrated Circuits Syst., 23, 519, 2004. With permission.) drive, so that sink/buffer capacitance can be incorporated. To keep the succinctness of the tile-based interval metric in Ref. [14], we discretize the load capacitance in units equivalent to the capacitance of wire with average tile size. Thus, we can prune out all intermediate solutions with load capacitance greater than U. During the bottom-up process, each intermediate solution is characterized by a 3-tuple s(vi , c, w) in which vi is the root of the subtree, c is the discretized load capacitance seen from vi , and w is the accumulated congestion cost. A solution can be pruned if both its c and w are no better than another one in the solution set associated with the same node vi . Starting from the leaf nodes, candidate solutions are generated and propagated toward the source in a bottom-up manner. Before we propagate candidate solutions from node vi to its parent node vj , we first find both plate P(vi ) and plate P(vj ) and define a bounding box that is the minimum-sized array of tiles covering both P(vi ) and P(vj ). Then we propagate all the candidate solutions from each tile of P(vi ) to each tile of P(vj ) within this bounding box. Because the Steiner nodes are more likely to be buffer sites due to the demand on decoupling noncritical branch load from the critical path, allowing Steiner nodes to be moved to less congested area is especially important. Moreover, such move is a part of a candidate solution, and therefore the move will be committed only when its corresponding candidate solution is finally selected at the driver. Thus, the tree adjustment is dynamically generated and selected according to the request of the final minimal congestion cost solution. 28.5.2.2 Hybrid Approach for Tree Adjustment Although the stage of plate-based tree adjustment effectively improve the layout congestion issue, there are several techniques [12] to improve the computational efficiency. Actually, the runtime bottleneck is due to the fact that buffering solution has to be searched along with node-to-node∗ paths in a two-dimensional plane because low congestion paths have to be found at where the buffers are needed. If we can predict where buffers are needed in advance, then we can merely focus on searching low congestion paths and the number of factors to be considered can be further reduced to one. If we ∗ The node may be the source node, a sink node, or a Steiner node of degree greater than two. Thus, degree-2 Steiner nodes are not included here. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 580 Finals Page 580 30-9-2008 #13 Handbook of Algorithms for Physical Design Automation diagnose the mechanism on how buffer insertion improves interconnect timing performance, it can be broken down into two parts: (1) regenerating signal level to increase driving capability for long wires and (2) shielding capacitive load at noncritical branches from the timing critical path. In a Steiner tree, buffers that play the first role are along a node-to-node path while buffers for the second purpose are normally close to a branching Steiner node. The majority of buffer insertion algorithms such as van Ginneken’s algorithm are dynamic programming based and have been proved to be very effective for both purposes. However, optimal buffer solutions along a node-to-node path can be found analytically [15,16]. This fact suggests that we may have a hybrid approach in which buffers along paths are placed according to the closed form solutions while the buffers at Steiner nodes are still solved by dynamic programming, i.e., analytical buffered path solutions replace both the wire segmenting [15] and candidate solution generations at segmenting points in the bottom-up dynamic programming framework. Computing candidate buffered paths analytically is faster than applying dynamic programming, which makes this hybrid approach more efficient than the purely dynamic programming scheme. It is also suggested in Ref. [12] that the plate should be selected as a set of nearby tiles with the least congestion because only the nearby tiles with relatively low buffer placement or routing congestion cost worth considering to be the alternative Steiner node. In fact, if there exists a tile with high congestion cost in the plate, it will never be used as the new Steiner node. Instead of using a length-based buffer insertion, the algorithm uses analytical formula for buffer insertion, which is separated from the minimum congestion cost path search process. If given the driver resistance, sink loading capacitance, and buffer resistance/capacitance/intrinsic delay, the optimal number of buffers and corresponding placement locations can be found with the equations [15], which are previously described in Section 26.2.1. We explain our buffered path routing technique by an example. For the thickened path in Figure 28.14a, if we know the driving resistance at v1 and load capacitance at v4 , we may obtain the optimal buffer positions at v2 and v3 . However, if we connect v1 and v4 in a two-dimensional plane, there are many alternative paths between them and the optimal buffer locations form rows along diagonal directions. The tiles for the optimal buffer locations are shaded in Figure 28.14a. Therefore, if we connect v1 and v4 with any monotone path and insert a buffer whenever this path passes through a shaded tile, the resulting buffered path should have the same minimum delay. The thin solid curve in Figure 28.14a is an example of an alternative minimum delay buffered path. Certainly, different buffer paths may have different congestion costs. Then the minimum congestion cost buffered path can be found by performing the Dijkstra’s algorithm on the tile graph, which is demonstrated in Figure 28.14b. In Figure 28.14b, each solid edge corresponds to a tile boundary and its edge cost is the corresponding wiring congestion cost. There are two types of nodes, the empty circle nodes that have zero cost and filled circle nodes that have cost equal to the placement congestion cost in v1 v1 v5 v6 v4 (a) v2 v3 v4 (b) FIGURE 28.14 Find low congestion path with known buffer positions indicated by the shaded tiles. (From figure 5 of Sze, C. -N., Hu, J., and Alpert, C. J., Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, 358, 2004. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C028 Buffering in the Layout Environment Finals Page 581 30-9-2008 #14 581 corresponding tile. In conclusion, the shortest path obtained in this way produces a buffered path with both good timing and low congestion cost. One of the issue related to the use of analytical formula is that the upstream resistance is unknown in the bottom-up solution propagation process. However, the lower bound on the upstream resistance is R = min(Rd , Rb ) and the upper bound R is max(Rd , Rb ) plus the upstream wire resistance.∗ Rd is the driver resistance and Rb is the buffer output resistance. Then, we can sample a few values between R and R, and find the minimum cost buffered path for each value. Because the timing result is not sensitive to the upstream resistance, normally the sampling size is very limited. 28.5.3 LAYOUT NAVIGATION To estimate the congestion efficiently, the solution quality of plate-based tree adjustment algorithms is restricted by the size of tile graph and the plate size. Because the complexity of the algorithm in Ref. [13] (described in Section 28.5.2.1) increases quadratically with plate size, using a fine tiling and a large plate size would be computationally prohibitive. More importantly, distinctions between critical and noncritical nets are missing in the algorithm. Practically, we may need to generate different solutions for critical and noncritical nets. To speed up the tree adjustment process, at most one candidate per tile is allowed, which results in a maze routing based algorithm [17]. The right cost function is paramount so as to maintain the quality. Moreover, instead of performing plate-to-plate routing of a sequence of tile-to-tile routes, the entire optimization is performed in a single pass. This allows one to use as large a plate as necessary, for almost no runtime penalty. During the maze routing-like process, an immediate solution only contains the cost information of the subtree. By parameterizing the cost function to trade off critical and noncritical nets, which leads to the algorithm in Ref. [18], we construct the cost function as follows, according to the criticality of the nets. For noncritical nets, some nets require buffering to fix electrical violations (such as slew, capacitance, or noise). Some other want the net to avoid highly dense areas or routing congestion. However, one still wants to minimize wirelength to some degree. So we set the cost to be 1 + e(gi ) and assume that the total tile congestion cost† e(gi ) is between 0 and 1, i.e., 0 ≤ e(gi ) ≤ 1. This implies that a tile blocked for routing or density has cost twice that of a tile that uses no resources. The constant of one can be viewed as a delay component. A tile that corresponds to a Steiner point must merge the costs of the children into a single cost, by simply adding up the cost functions of all the children. Because these are noncritical nets, all sinks are treated equally by having initial cost zero. For critical nets, the cost impact of the environment is immaterial. We seek the absolutely best possible slack. When a net is optimally buffered (assuming no obstacles), its delay is a linear function of its length [19]. Hence, to minimize delay, we simply minimize the number of tiles to the most critical sink, which results in a unit cost defined for each tile. When merging the branches, we pick the branch with worst slack, so the merged cost is the maximum of both costs. The costs at sinks are initialized based on the sink criticality. The more critical a sink, the higher its initial cost. Finally, the objective is to minimize cost at the source. The algorithm is able to the trade off between the critical and noncritical cost functions during the maze routing procedure. Let 0 ≤ K ≤ 1 be the trade-off parameter, where K = 1 corresponds to a noncritical net and K = 0 corresponds to a critical net. On the basis of the previously defined cost functions for noncritical and critical nets, the cost function for a tile gi is then 1 + K · e(gi ). For critical nets, merging branches is a maximization function, while it is an additive function for noncritical nets. These ideas can be combined while the merging cost of two children gi and gj becomes max[cost(gi ), cost(gj )] + K · min[cost(gi ), cost(gj )]. ∗ † The maximum upstream wire resistance can be derived from the length of maximum buffer-to-buffer interval. This is also mentioned in Ref. [14]. The total congestion cost of a tile can be a linear expression of the squares of tile density and all its boundary densities.

Handbook of algorithms for physical design automation part 60

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